SpicaWorks is hiring the following Skills interested hurry up and share your resume to krishnapriya@spicaworks.com

Design Verification : 4+ years (Strong in SV ,UVM) ( Immediate /Notice Period )
Physical Design : 4+ years ( Immediate /Notice Period )
DFT Engineers : 3+ years ( Immediate /Notice Period )
Physical Verifications : 4+ years ( Immediate /Notice Period )
AMS Verification : 4+ years (Immediate /15 days )

#verification #systemverilog #uvm #pcie #designverification #asicdesign #ovm #dv #ddr #ethernet #socverification #asicverification #physicaldesign #pd #icc #icc2 #primetime #sta #synthesis #DFT #atpg #mbist #physicalverification

We have job openings with leading product based companies for the below skills-at Bangalore.

Requirements:

ASIC Design Manager: 15+yrs
ASIC Verification Manager: 13+yrs
ASIC Design: 6+yrs
Circuit Design: 5+years
Verification: 5+yrs
Physical Verification(AE): 6+yrs
DFT Engineer: 4+yrs
PCB Design(AE): 4+yrs

Work Location: Bangalore

If interested candidates please share their CV to my mail id - daicy.ramesh@careernet.co.in

#vlsijobs #semiconductors #fulltimejob #design #rtldesign #sv #ddr #pcie #uvm #physicalverification #asic #dft #pcbdesign #bangalorejobs

Cadence Design Systems looking for Lead #asicverificationengineer for #pune location #xtensaprocessor #uvm #systemverilog
interested one can share your resume with me furkank@cadence.com

Hiring for VLSI Verification (ASIC/SOC) <<<
Trained candidates are preferable
#Eligibility : M-tech(2016,17,18,19 &20), B-tech(2016,17 & 18) only.
#verilog hashtag
#systemverilog hashtag
#uvm
1. Worked on SV and UVM test bench.
2. Good knowledge of Functional coverage, Code Coverage, Assertions, Constraints.
3. Good communication skills.
Basic hashtag
#knowledge on protocols like AXI, AHB, APB etc
Interested Candidates can send their Resumes to rajasri@atrialogic.com

We are looking for Key Openings with our Prestigious Clients in Bangalore, Hyderabad, Pune, Noida.
If you wish to explore, Please share your CV @ newsoft@nsoftindia.com to discuss further details...

#RTL #Verification #STA #UVM #SystemVerilog #DFT #ATPG #LBIST #MBIST #SCAN #JTAG #Validation #PhysicalDesign #PHP, #Python #MachineLearning #ComputerVision

Designation - Sr. Engineer, Tech Lead, Architect, Project Manager
Location - Bangalore, Hyderabad, Pune, Noida
Exp. – 3-15 Years

Open Position -
1. RTL Design [4-15 Years]
2. Verification [SoC/ IP/ AMS] [3-15 Years]
3. STA [4-10 Years]
4. DFT [ATPG, SCAN, DFT] [3-12 Years]
5. Physical Design [3-12 Years]
6. Post Si. Validation [5-15 Years]
7. Compiler Development [2-6 Years]
8. C++, CUDA, Python [3-8 Years]
9. Machine Learning Framework Development [3-8 Years]
10. Android Framework Development [3-8 Years]
11. PHP Developer [3-7 Years]

HR at Gangaaram Technologies PVT LTD Tirupati
Hiring for VLSI Verification (ASIC/SOC) <<<
Trained candidates are preferable
#Eligibility : M-tech(2016,17,18,19 &20), B-tech(2016,17 & 18) only.
#verilog hashtag
#systemverilog hashtag
#uvm
1. Worked on SV and UVM test bench.
2. Good knowledge of Functional coverage, Code Coverage, Assertions, Constraints.
3. Good communication skills.
Basic hashtag
#knowledge on protocols like AXI, AHB, APB etc
Interested Candidates can send their Resumes to rajasri@atrialogic.com

#URGENTLY Hiring- Verification Lead -USB, PCIe, Ethernet, DDR (4-15 Yrs) in Bangalore, Hyderabad, Noida; Please share your CV @ newsoft@nsoftindia.com to discuss...
#hiring #Verification #UVM #Verilog #SystemVerilog #USB #DDR #PCIe #Ethernet #AXI #AHB

https://lnkd.in/dtakdDH

Hiring for one of our client in Bangalore for Design Verification role with US based product development company.
#designverification #soc #IP #UVM, #OVM #RTL, #ARMbased
Job Location: Bangalore
Company: US based MNC Product based company
Experience required - 5+ years Sr Design Verification
10+ years for Lead design verification
15+ years of Manager design verification

Have you developed SOC-level test benches & what components of test bench did you developed?
Have you Verified ARM-based IP/SOC ?
Have you created SOC-level test-cases and debugged them.
Have you developed IP-level test benches ? If so, what components of test bench did they develop expertise with UVM verification methodology ? i.e
How many UVM test benches and/or verification components did you created ?
If anyone having the experience into above mentioned questions, please share your resume at isha@eftihiaindia.com.

Bitsilica is Hiring VLSI Trained M.Tech Freshers (2020/2019/2018) / B.Tech ( 2019/2018/2017) & Experienced Engineers

Location: hyderabad / bangalore

Job Details:

Skilled in #systemverilog #uvm #verilog #vhdl
Good Knowledge on high speed #protocols

Interested professionals share ur profile to
careers@bitsilica.com

Bitsilica is Hiring VLSI Trained M.Tech Freshers (2020/2019/2018) / B.Tech ( 2019/2018/2017) & Experienced Engineers

Location: hyderabad / bangalore

Job Details:

Skilled in #systemverilog #uvm #verilog #vhdl
Good Knowledge on high speed #protocols

Interested professionals share ur profile to
careers@bitsilica.com

Hi All,
Greetings from ACL Digital!!
Hiring for VLSI Engineers for Bangalore and Hyderabad locations.

SOC/ IP Verification - 5+ years
Physical Design- 5+ years
DFT Engineer- 5+ years
ASIC RTL Design- 8+ years

#UVM #Verilog #SV #SOC #IP #PCIE #ASIC #VLSI #physicaldesign #sta #lvs #drc #lint #cdc #asicdesign
Kindly share resumes to chiranjeevi.k@acldigital.com