We are hiring #VLSI Engineers

> ASIC Verification
> Physical Design
> DFT
> FPGA Design Verification

Experience : 4-10 years
Location : #Bengaluru

Interested candidates can share updated resumes to ar@radiantsemi.com

Senior #Recruiter opportunity[2-5yrs] [#VLSI/#Semiconductor/#Embedded background]@ Bharat headhunters : Hiring for product companies. Interested, kindly share your profile to gopinath@bharatheadhunters.com

Greetings from SIART DESIGN SYSTEMS, Bangalore, India !!

We have an opening for 3 to 8 years experienced Physical Design Engineers who can join immediately or within 15-20 days.

Job Description:
Working on 16nm and below advanced process project APR and sign-off
Take the TOP and PM role for the complicated hierarchical chip (more than 20m plus 500+ macros)
Take the Block coordinator role for more than 10 blocks, solving the critical issue and give the solution to block owner
Do early prediction for critical issues when project start
Requirement
APR hands-on experience with complicated hierarchical chip (more than 20m instance)
TCL/Perl/script/C/C++ programming skill
Have advanced process tapeout experience (T6 is needed, and N7 is a plus)
Excellent communication

Interested can share their CV at hr@siartdesign.com

#job #bangalore #design #vlsi #physicaldesign @Bengaluru_Jobs
#physicalverification #hardware #engineer #urgent #immediate #semiconductor #apr #perl #c++ #script #tcl #c

#Wipro currently Hiring for #vlsi #Engineers for below skills
#experience : 4+yrs
#bangalore #cochin #pune #hyderabad #greaternoida

#physicaldesign
#designverification
#verification
#dft
#sta
#rtldesign
#asicdesign
#fpgadesign with #3GPP

Interested Applicants can share resumes to email ID: mohammed.umar3@wipro.com

I am #Hiring for Top Product Based MNC (#Semiconductor company) for #Bangalore, #Hyderabad & #Chennai Location

#GLV - Gate Level Verification Engineer with 5-9yrs – Bangalore Location
#RTL Design Engineer with 5-9yrs – Bangalore Location
#Validation Engineer (with #LabView and #TestStand ) with 1-3yrs – Bangalore Location
#PSV -Silicon Validation Engineer with 5-8yrs – Hyderabad Location
#CAE - Embedded Application Engineer with 4-12yrs – Chennai Location
#Analoglayout Engineer with 5-8yrs – Hyderabad Location

Interested candidates please drop your CV to sst2@aimplusstaffing.com

#vlsi #verification #rtl, #validation, #designengineer #embeddedsoftware #analogdesign

Warm Regards,
Poojary Deepika |Senior Recruitment Executive
|https://lnkd.in/g2-xcAE

Aim Plus Staffing Solutions - Bangalore | New Delhi

#Hiring #VLSI #PD #RTL #FPGA #Analog #Memory #validation #vlsijobs
https://www.instagram.com/p/CP_vDR1h1O1/?utm_medium=share_sheet

#Hiring #VLSI #RTL #PD #Memory #DFT #Analog #Verification #Semiconductor #VLSIjobs #vlsidesign
https://www.instagram.com/p/CQDEBOohgdY/?utm_medium=share_sheet

Hi All,
Greetings from ACL Digital!!
Hiring for VLSI Engineers for Bangalore and Hyderabad locations.

SOC/ IP Verification - 5+ years
Physical Design- 5+ years
DFT Engineer- 5+ years
ASIC RTL Design- 8+ years

#UVM #Verilog #SV #SOC #IP #PCIE #ASIC #VLSI #physicaldesign #sta #lvs #drc #lint #cdc #asicdesign
Kindly share resumes to chiranjeevi.k@acldigital.com

Dear Folks,

We at HCLTech are hiring for #Design_Verification (#VLSI skill)

Job Location : Bangalore / Noida / Chennai / Cochin

Skills expertise : UVM, System Verilog, IP logic, SOC Verification

Notice Period : Immediate Joiners will be preferred but 90 days notice period can also be considered

Aspirants, with the relevant skills set please share your updated resume at mona.dubey@hcl.com

Hi All,

Ignitarium is hosting a weekend drive for various positions in #VLSI at the #Bangalore and #Kochi locations. If you have experience in the following roles, we want to hear from you:

- Design Verification (3+ Years)
- Physical Verification (4+ Years)
- Physical Design Lead (8+ years)
- Physical Design Engineer (3+ Years with Cadence tool Exp)
- RTL/ASIC Design Engineer (3+ Years)
- RTL Lead (7+ years)

To apply, kindly send your resumes to akhila.babu@ignitarium.com.
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