XILINX,Hyderabad Hiring engineers with the following skills.

1)Physical design Manager :13-18Yrs
2)STA : (13+years)
3)FPGA Prototyping,Emulation:12+Yrs
4) IP Verification Engineers :5+Yrs
5) Post Silicon validation ,PCIE: 7+Yrs
6) PCB Package : 12+Yrs
7) DDR Verification :5+Yrs
8) MIPI Verification : 6+Yrs
9) Coherency Verification :12+Yrs
10)EDA Software Engineer :3+Yrs
11) Emulation Lead :13+yrs
12) RTL Design :4+Yrs
13) Embedded Device driver developer : 7+Yrs
14) Physical Design : 5+Yrs
15)Machine learning :4+Yrs

# #verification #pcie #systemverilog #uvm #systemverilog #ethernet #xilinxhyderabad #physicaldesign #sta #timinganalysis #fpgaprototype #fpgavalidation #pnrcad #rtldesign #dft #fullcustomdesign

Interested candidates can reachout to shalini.recharla@xilinx.com

SpicaWorks is hiring the following Skills interested hurry up and share your resume to krishnapriya@spicaworks.com

Design Verification : 4+ years (Strong in SV ,UVM) ( Immediate /Notice Period )
Physical Design : 4+ years ( Immediate /Notice Period )
DFT Engineers : 3+ years ( Immediate /Notice Period )
Physical Verifications : 4+ years ( Immediate /Notice Period )
AMS Verification : 4+ years (Immediate /15 days )

#verification #systemverilog #uvm #pcie #designverification #asicdesign #ovm #dv #ddr #ethernet #socverification #asicverification #physicaldesign #pd #icc #icc2 #primetime #sta #synthesis #DFT #atpg #mbist #physicalverification

Cadence Design Systems looking for Lead #asicverificationengineer for #pune location #xtensaprocessor #uvm #systemverilog
interested one can share your resume with me furkank@cadence.com

Hiring for VLSI Verification (ASIC/SOC) <<<
Trained candidates are preferable
#Eligibility : M-tech(2016,17,18,19 &20), B-tech(2016,17 & 18) only.
#verilog hashtag
#systemverilog hashtag
#uvm
1. Worked on SV and UVM test bench.
2. Good knowledge of Functional coverage, Code Coverage, Assertions, Constraints.
3. Good communication skills.
Basic hashtag
#knowledge on protocols like AXI, AHB, APB etc
Interested Candidates can send their Resumes to rajasri@atrialogic.com

We are looking for Key Openings with our Prestigious Clients in Bangalore, Hyderabad, Pune, Noida.
If you wish to explore, Please share your CV @ newsoft@nsoftindia.com to discuss further details...

#RTL #Verification #STA #UVM #SystemVerilog #DFT #ATPG #LBIST #MBIST #SCAN #JTAG #Validation #PhysicalDesign #PHP, #Python #MachineLearning #ComputerVision

Designation - Sr. Engineer, Tech Lead, Architect, Project Manager
Location - Bangalore, Hyderabad, Pune, Noida
Exp. – 3-15 Years

Open Position -
1. RTL Design [4-15 Years]
2. Verification [SoC/ IP/ AMS] [3-15 Years]
3. STA [4-10 Years]
4. DFT [ATPG, SCAN, DFT] [3-12 Years]
5. Physical Design [3-12 Years]
6. Post Si. Validation [5-15 Years]
7. Compiler Development [2-6 Years]
8. C++, CUDA, Python [3-8 Years]
9. Machine Learning Framework Development [3-8 Years]
10. Android Framework Development [3-8 Years]
11. PHP Developer [3-7 Years]

HR at Gangaaram Technologies PVT LTD Tirupati
Hiring for VLSI Verification (ASIC/SOC) <<<
Trained candidates are preferable
#Eligibility : M-tech(2016,17,18,19 &20), B-tech(2016,17 & 18) only.
#verilog hashtag
#systemverilog hashtag
#uvm
1. Worked on SV and UVM test bench.
2. Good knowledge of Functional coverage, Code Coverage, Assertions, Constraints.
3. Good communication skills.
Basic hashtag
#knowledge on protocols like AXI, AHB, APB etc
Interested Candidates can send their Resumes to rajasri@atrialogic.com

#URGENTLY Hiring- Verification Lead -USB, PCIe, Ethernet, DDR (4-15 Yrs) in Bangalore, Hyderabad, Noida; Please share your CV @ newsoft@nsoftindia.com to discuss...
#hiring #Verification #UVM #Verilog #SystemVerilog #USB #DDR #PCIe #Ethernet #AXI #AHB

https://lnkd.in/dtakdDH

Bitsilica is Hiring VLSI Trained M.Tech Freshers (2020/2019/2018) / B.Tech ( 2019/2018/2017) & Experienced Engineers

Location: hyderabad / bangalore

Job Details:

Skilled in #systemverilog #uvm #verilog #vhdl
Good Knowledge on high speed #protocols

Interested professionals share ur profile to
careers@bitsilica.com

Bitsilica is Hiring VLSI Trained M.Tech Freshers (2020/2019/2018) / B.Tech ( 2019/2018/2017) & Experienced Engineers

Location: hyderabad / bangalore

Job Details:

Skilled in #systemverilog #uvm #verilog #vhdl
Good Knowledge on high speed #protocols

Interested professionals share ur profile to
careers@bitsilica.com