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Author and maintainer: https://github.com/katursis
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#assembly #cpu #fpga #riscv #soc #softcore #spinalhdl #verilog #vhdl

This repository provides a highly configurable RISC-V CPU implementation written in SpinalHDL. Here are the key benefits and features The CPU can be customized with various plugins to add or remove features such as instruction and data caches, multiplication and division units, floating-point units, and more.
- **Performance** It includes a debug module that allows for Eclipse debugging via GDB, OpenOCD, and JTAG connections.
- **Compatibility** The CPU can be optimized for different FPGA targets, and it does not use any vendor-specific IP blocks.
- **Extensibility**: New instructions and peripherals can be added easily through the plugin system, making it highly extensible.

Overall, this implementation offers a flexible and powerful RISC-V CPU solution that can be tailored to various needs and applications.

https://github.com/SpinalHDL/VexRiscv
#yara #awesome_list #blueteam #blueteam_tools #cti #detection #detection_engineering #dfir #hacktools #incident_response #ioc #iocs #ir #ransomware #redteam #rmm #security #siem #soc #threat_hunting #threat_intelligence

You can access comprehensive security detection lists and threat hunting resources that help identify malicious activity across your infrastructure. These curated collections include indicators like suspicious file hashes, domain names, IP addresses, and behavioral patterns organized by threat type—from ransomware and phishing to command-and-control servers and vulnerable drivers. By integrating these lists into your security tools like SIEM platforms and endpoint detection systems, you gain immediate visibility into known threats while learning detection methodologies through guides and YARA rules. This accelerates your ability to hunt for compromises, validate security controls, and stay current with emerging attack techniques without building detection logic from scratch.

https://github.com/mthcht/awesome-lists