#assembly #cpu #fpga #riscv #soc #softcore #spinalhdl #verilog #vhdl

This repository provides a highly configurable RISC-V CPU implementation written in SpinalHDL. Here are the key benefits and features The CPU can be customized with various plugins to add or remove features such as instruction and data caches, multiplication and division units, floating-point units, and more.
- **Performance** It includes a debug module that allows for Eclipse debugging via GDB, OpenOCD, and JTAG connections.
- **Compatibility** The CPU can be optimized for different FPGA targets, and it does not use any vendor-specific IP blocks.
- **Extensibility**: New instructions and peripherals can be added easily through the plugin system, making it highly extensible.

Overall, this implementation offers a flexible and powerful RISC-V CPU solution that can be tailored to various needs and applications.

https://github.com/SpinalHDL/VexRiscv

#c_lang #aarch64 #arm #arm64 #bios #boot_loader #boot_manager #bootloader #efi #gpt #loongarch #loongarch64 #loongson #mbr #risc_v #riscv #riscv64 #uefi #x64 #x86 #x86_64

Limine is a modern bootloader that boots Linux and other OSes on x86, ARM64, RISC-V, and LoongArch64 hardware, supporting MBR/GPT partitions and FAT/ISO filesystems on 32-bit Pentium Pro+ or 64-bit systems. Get binaries via Git (e.g., `git clone --branch=v11.x-binary`), build tools with `make`, and join Matrix/Fluxer chats for help. This lets you easily manage and boot multiple OSes with a clean menu, saving time on custom PC or server setups.

https://github.com/Limine-Bootloader/Limine