Samsung Semiconductor India R&D, Hiring for...


1) RTL - SoC Integration Engineer - Experience 5-12 Years
Exp in Synthesis, CDC LINT Spyglass

2) Analog Layout Engineer - Experience 4-7 Years
Exp in Layout design(only ADC, DAC)

Interested candidates kindly send your profiles to my "Linked-in-Inbox / rajkumar.p@partner.samsung.com"

#RTL_Integration, #Analog_Layout

Tessolve is hiring!!!

#DFT Manager/Lead - 10+ years
#DFT engineers - 3+years
#Physical Design (PD) - Lead - 10+years
#Physical Design/STA - 3+years
#Design Verification (DV)-SOC/IP - 3+years
#DV Lead - 10+years
#Analog layout - 3+years
#circuit design - 3+years


Interested or have any reference?- Please reach out to heena.mahajan@tessolve.com