#Eximius have Great opportunity to explore your skills
Hiring #Design Verification Engineers for #Bangalore, #Hyderabad, #Ahmedabad, #Cochin and #Pune Locations with the Experience of #5 to 15 Years.
Interested Kindly share your updated resume to #seemabr@eximiusdesign.com
Thanks and Regards,
Seema BR
Hiring #Design Verification Engineers for #Bangalore, #Hyderabad, #Ahmedabad, #Cochin and #Pune Locations with the Experience of #5 to 15 Years.
Interested Kindly share your updated resume to #seemabr@eximiusdesign.com
Thanks and Regards,
Seema BR
Tessolve is hiring!!!
#DFT Manager/Lead - 10+ years
#DFT engineers - 3+years
#Physical Design (PD) - Lead - 10+years
#Physical Design/STA - 3+years
#Design Verification (DV)-SOC/IP - 3+years
#DV Lead - 10+years
#Analog layout - 3+years
#circuit design - 3+years
Interested or have any reference?- Please reach out to heena.mahajan@tessolve.com
#DFT Manager/Lead - 10+ years
#DFT engineers - 3+years
#Physical Design (PD) - Lead - 10+years
#Physical Design/STA - 3+years
#Design Verification (DV)-SOC/IP - 3+years
#DV Lead - 10+years
#Analog layout - 3+years
#circuit design - 3+years
Interested or have any reference?- Please reach out to heena.mahajan@tessolve.com
SpicaWorks is hiring #Design_Verification_Engineers
Interested candidate share your resume to james.paul@spicaworks.com
Experience - 3 -15 Years
Skills: Expert in developing test bench/test case using System Verilog & UVM/OVM
Job Location - #Bangalore/ #Hyderabad/ #Noida
Interested candidate share your resume to james.paul@spicaworks.com
Interested candidate share your resume to james.paul@spicaworks.com
Experience - 3 -15 Years
Skills: Expert in developing test bench/test case using System Verilog & UVM/OVM
Job Location - #Bangalore/ #Hyderabad/ #Noida
Interested candidate share your resume to james.paul@spicaworks.com
Forwarded from Chennai Jobs & Careers (Siva Ganesan)
Dear Folks,
We at HCLTech are hiring for #Design_Verification (#VLSI skill)
Job Location : Bangalore / Noida / Chennai / Cochin
Skills expertise : UVM, System Verilog, IP logic, SOC Verification
Notice Period : Immediate Joiners will be preferred but 90 days notice period can also be considered
Aspirants, with the relevant skills set please share your updated resume at mona.dubey@hcl.com
We at HCLTech are hiring for #Design_Verification (#VLSI skill)
Job Location : Bangalore / Noida / Chennai / Cochin
Skills expertise : UVM, System Verilog, IP logic, SOC Verification
Notice Period : Immediate Joiners will be preferred but 90 days notice period can also be considered
Aspirants, with the relevant skills set please share your updated resume at mona.dubey@hcl.com