XILINX,Hyderabad Hiring engineers with the following skills.

1)Physical design Manager :13-18Yrs
2)STA : (13+years)
3)FPGA Prototyping,Emulation:12+Yrs
4) IP Verification Engineers :5+Yrs
5) Post Silicon validation ,PCIE: 7+Yrs
6) PCB Package : 12+Yrs
7) DDR Verification :5+Yrs
8) MIPI Verification : 6+Yrs
9) Coherency Verification :12+Yrs
10)EDA Software Engineer :3+Yrs
11) Emulation Lead :13+yrs
12) RTL Design :4+Yrs
13) Embedded Device driver developer : 7+Yrs
14) Physical Design : 5+Yrs
15)Machine learning :4+Yrs

# #verification #pcie #systemverilog #uvm #systemverilog #ethernet #xilinxhyderabad #physicaldesign #sta #timinganalysis #fpgaprototype #fpgavalidation #pnrcad #rtldesign #dft #fullcustomdesign

Interested candidates can reachout to shalini.recharla@xilinx.com

SpicaWorks is hiring the following Skills interested hurry up and share your resume to krishnapriya@spicaworks.com

Design Verification : 4+ years (Strong in SV ,UVM) ( Immediate /Notice Period )
Physical Design : 4+ years ( Immediate /Notice Period )
DFT Engineers : 3+ years ( Immediate /Notice Period )
Physical Verifications : 4+ years ( Immediate /Notice Period )
AMS Verification : 4+ years (Immediate /15 days )

#verification #systemverilog #uvm #pcie #designverification #asicdesign #ovm #dv #ddr #ethernet #socverification #asicverification #physicaldesign #pd #icc #icc2 #primetime #sta #synthesis #DFT #atpg #mbist #physicalverification

We have job openings with leading product based companies for the below skills-at Bangalore.

Requirements:

ASIC Design Manager: 15+yrs
ASIC Verification Manager: 13+yrs
ASIC Design: 6+yrs
Circuit Design: 5+years
Verification: 5+yrs
Physical Verification(AE): 6+yrs
DFT Engineer: 4+yrs
PCB Design(AE): 4+yrs

Work Location: Bangalore

If interested candidates please share their CV to my mail id - daicy.ramesh@careernet.co.in

#vlsijobs #semiconductors #fulltimejob #design #rtldesign #sv #ddr #pcie #uvm #physicalverification #asic #dft #pcbdesign #bangalorejobs

Greetings from Cerium-TechMahindra!

Immediate hiring for

#Verification
#Memory Layout
#Memory Design
#RTL Design
#Physical Design
#DFT
#FPGA

Experience: 3+years
Work Location: Bangalore/Hyderabad/Chennai/Kochi/Ahmedabad/Vizag

If interested, please share your updated resume on gk00725438@techmahindra.com

Greetings from Tech_Mahindra-Cerium Systems!!

We are currently Hiring for
Physical Design (5-15years)
#DFT (3-15 years)
#RTLDesign and #Verification(4-15 years)
#Emulation_Engineer (2-15 years)

Location: Bangalore/Chennai/Hyderabad/Vizag/Kocchi/Ahmedabad
/Penang(Malaysia)
( #H1Bvisa will be sponsored)

Interested candidates can share your updated CV to ''sm00728691@techmahindra.com''

Regards,
Shanawaz M

#AMD #hiring #DFT #ATPG #MBIST #JTAG #5years #Bangalore

Please send your resumes to shobana.kannan@amd.com

#Wipro currently Hiring for #vlsi #Engineers for below skills
#experience : 4+yrs
#bangalore #cochin #pune #hyderabad #greaternoida

#physicaldesign
#designverification
#verification
#dft
#sta
#rtldesign
#asicdesign
#fpgadesign with #3GPP

Interested Applicants can share resumes to email ID: mohammed.umar3@wipro.com

We have the open positions if interested share the CV to below ID
JP00730628@TechMahindra.com
#DFT : 3 to 18 Yrs
#PD : 5 to 18Yrs
#DV : 5 to 18Yrs
#FPGA /RTL : 5 to 18 Yrs,
#STA : 3 to 18Yrs
JP00730628@TechMahindra.com

#Excellent Opportunity For #M.Tech #Trained #Freshers For Noida And Bangalore Location :

1: #RTL Design Engineer ( #Noida Location)
2: #Verification Engineer ( #Noida Location)
3: #DFT Engineer ( #Bangalore Location)
4: #Embedded Engineer ( #Noida Location, #Preferred if you are in #North Location only)
5: #Physical Design Engineers ( #Noida Location, Preferred if you are in #North Location only)

Please share your resume on madhuri.tomar@incise.in
#Incise #embeddedsystems #embeddedjobs #noida #embeddedsoftware #freshersopportunity #vlsijobs #rtldesign #verifications #physicaldesign #freshersjob #fresherhiring

We are looking for Key Openings with our Prestigious Clients in Bangalore, Hyderabad, Pune, Noida.
If you wish to explore, Please share your CV @ newsoft@nsoftindia.com to discuss further details...

#RTL #Verification #STA #UVM #SystemVerilog #DFT #ATPG #LBIST #MBIST #SCAN #JTAG #Validation #PhysicalDesign #PHP, #Python #MachineLearning #ComputerVision

Designation - Sr. Engineer, Tech Lead, Architect, Project Manager
Location - Bangalore, Hyderabad, Pune, Noida
Exp. – 3-15 Years

Open Position -
1. RTL Design [4-15 Years]
2. Verification [SoC/ IP/ AMS] [3-15 Years]
3. STA [4-10 Years]
4. DFT [ATPG, SCAN, DFT] [3-12 Years]
5. Physical Design [3-12 Years]
6. Post Si. Validation [5-15 Years]
7. Compiler Development [2-6 Years]
8. C++, CUDA, Python [3-8 Years]
9. Machine Learning Framework Development [3-8 Years]
10. Android Framework Development [3-8 Years]
11. PHP Developer [3-7 Years]

#Excellent Opportunity For #M.Tech #Trained #Freshers For Noida And Bangalore Location :

1: #RTL Design Engineer ( #Noida Location)
2: #Verification Engineer ( #Noida Location)
3: #DFT Engineer ( #Bangalore Location)
4: #Embedded Engineer ( #Noida Location, #Preferred if you are in #North Location only)
5: #Physical Design Engineers ( #Noida Location, Preferred if you are in #North Location only)

Please share your resume on madhuri.tomar@incise.in

Hi All,
ALTEN Calsoft Labs is hiring for DFT Engineers for Bangalore location.
Exp: 3 to 5 years
DFT and ATPG with SCAN insertion experience .
#DFT #ATPG #scaninsertion #jtag
Interested, kindly share resumes to saisruthi.t@acldigital.com

#Excellent Opportunity For #M.Tech #Trained #Freshers For #Noida Location :

1: #RTL Design Engineer
2: #Verification Engineer
3: #DFT Engineer
4: #Embedded Engineer ( #Preferred if you are in #North Location only)
5: #Physical Design Engineers (Preferred if you are in #North Location only)

Please share your resume on madhuri.tomar@incise.in

#Excellent Opportunity For #M.Tech #Trained #Freshers For Noida Location :

1: #RTL Design Engineer
2: #Verification Engineer
3: #DFT Engineer
4: #Embedded Engineer ( #Preferred if you are in #North Location only)
5: #Physical Design Engineers ( Preferred if you are in #North Location only)

Please share your resume on Shubhanshi@incise.in

#Hiring #VLSI #RTL #PD #Memory #DFT #Analog #Verification #Semiconductor #VLSIjobs #vlsidesign
https://www.instagram.com/p/CQDEBOohgdY/?utm_medium=share_sheet

Tessolve is hiring!!!

#DFT Manager/Lead - 10+ years
#DFT engineers - 3+years
#Physical Design (PD) - Lead - 10+years
#Physical Design/STA - 3+years
#Design Verification (DV)-SOC/IP - 3+years
#DV Lead - 10+years
#Analog layout - 3+years
#circuit design - 3+years


Interested or have any reference?- Please reach out to heena.mahajan@tessolve.com

Excelmax Technologies is hiring for
#dft engineers for Bangalore location, interested engineers please share cv to suman@excelmaxtech.com
Exp : 8+ Years
NP : Immediate to 30days