#Immediate opportunities for Verification #freshers
Please share and like to help freshers.
Requirements:
- Trained or did an Internship in #Verification.
- Have strong knowledge in System Verilog, #Digital electronics, #Verilog.
- Good communication skills.
- Open for #Noida Location.

If you have all the above requirements, please share your resume on shubhanshi@incise.in

Hiring for VLSI Verification (ASIC/SOC) <<<
Trained candidates are preferable
#Eligibility : M-tech(2016,17,18,19 &20), B-tech(2016,17 & 18) only.
#verilog hashtag
#systemverilog hashtag
#uvm
1. Worked on SV and UVM test bench.
2. Good knowledge of Functional coverage, Code Coverage, Assertions, Constraints.
3. Good communication skills.
Basic hashtag
#knowledge on protocols like AXI, AHB, APB etc
Interested Candidates can send their Resumes to rajasri@atrialogic.com

HR at Gangaaram Technologies PVT LTD Tirupati
Hiring for VLSI Verification (ASIC/SOC) <<<
Trained candidates are preferable
#Eligibility : M-tech(2016,17,18,19 &20), B-tech(2016,17 & 18) only.
#verilog hashtag
#systemverilog hashtag
#uvm
1. Worked on SV and UVM test bench.
2. Good knowledge of Functional coverage, Code Coverage, Assertions, Constraints.
3. Good communication skills.
Basic hashtag
#knowledge on protocols like AXI, AHB, APB etc
Interested Candidates can send their Resumes to rajasri@atrialogic.com

#URGENTLY Hiring- Verification Lead -USB, PCIe, Ethernet, DDR (4-15 Yrs) in Bangalore, Hyderabad, Noida; Please share your CV @ newsoft@nsoftindia.com to discuss...
#hiring #Verification #UVM #Verilog #SystemVerilog #USB #DDR #PCIe #Ethernet #AXI #AHB

https://lnkd.in/dtakdDH

Bitsilica is Hiring VLSI Trained M.Tech Freshers (2020/2019/2018) / B.Tech ( 2019/2018/2017) & Experienced Engineers

Location: hyderabad / bangalore

Job Details:

Skilled in #systemverilog #uvm #verilog #vhdl
Good Knowledge on high speed #protocols

Interested professionals share ur profile to
careers@bitsilica.com

Bitsilica is Hiring VLSI Trained M.Tech Freshers (2020/2019/2018) / B.Tech ( 2019/2018/2017) & Experienced Engineers

Location: hyderabad / bangalore

Job Details:

Skilled in #systemverilog #uvm #verilog #vhdl
Good Knowledge on high speed #protocols

Interested professionals share ur profile to
careers@bitsilica.com

Hi All,
Greetings from ACL Digital!!
Hiring for VLSI Engineers for Bangalore and Hyderabad locations.

SOC/ IP Verification - 5+ years
Physical Design- 5+ years
DFT Engineer- 5+ years
ASIC RTL Design- 8+ years

#UVM #Verilog #SV #SOC #IP #PCIE #ASIC #VLSI #physicaldesign #sta #lvs #drc #lint #cdc #asicdesign
Kindly share resumes to chiranjeevi.k@acldigital.com