Greetings from SIART DESIGN SYSTEMS, Bangalore, India !!

We have an opening for 3 to 8 years experienced Physical Design Engineers who can join immediately or within 15-20 days.

Job Description:
Working on 16nm and below advanced process project APR and sign-off
Take the TOP and PM role for the complicated hierarchical chip (more than 20m plus 500+ macros)
Take the Block coordinator role for more than 10 blocks, solving the critical issue and give the solution to block owner
Do early prediction for critical issues when project start
Requirement
APR hands-on experience with complicated hierarchical chip (more than 20m instance)
TCL/Perl/script/C/C++ programming skill
Have advanced process tapeout experience (T6 is needed, and N7 is a plus)
Excellent communication

Interested can share their CV at hr@siartdesign.com

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